An important aspect in many manufacturing processes is the testing of the manufactured products. Testing is utilized to verify that the manufactured products function and operate properly and perform in accordance with the specifications set forth by the product design. There are often a plurality of tests which may be performed on the product or products at different points or stages in the manufacturing process. For example, after a particular sub-assembly of a product is manufactured, there may be tests performed to verify the specific functions of the sub-assembly prior to its incorporation into an overall final product. In addition to or oftentimes as a preferred alternative to separate testing of the sub-assemblies or sub-components, there may be tests that can be performed on the final overall completed product including the one or more sub-components after the final step of the manufacturing/assembling process.
In order to meet an ever increasing demand of consumers for the latest high technology products, manufacturers are forced to constantly design and deliver these new products to the marketplace in an ever decreasing time span. Techniques that shorten the time needed to bring a product to market can provide a competitive advantage over competitors who do not have access to such techniques. Consequently, any such techniques or mechanisms to shorten the time-to-market are desirable and may be readily accepted by manufacturers.
Shortening the total test time required to adequately test the functionality of the manufactured products is one way to decrease the time required to bring a new product to market. The total test time may typically be a function of one or more factors, e.g.: (1) the run time of the test, i.e., the time it takes to actually perform a particular test on the device, and (2) the test set-up time, i.e., the time it takes to configure and set-up the test equipment to perform the test. Thus, in order to decrease the total test time, it is desirable to find ways to shorten either or both of the run time and/or the set-up times of the tests.
Heretofore, integrated circuit (IC) and/or system on a chip (SOC) devices have been tested and verified using a variety of test methods. In some examples, IC and/or SOC devices have been tested and verified to be defect free using functional test vectors, such as those applied to the IC and/or SOC by the use of automated test equipment (ATE), which stimulate and verify the IC/SOC device functionality at the pin-level of the device. A practical limitation to the utilization of ATE for testing ICs or SOCs, however, is the identification and verification of the proper port assignments of IC/SOC pins (or pads) that are to be tested by a particular ATE. This has, heretofore, been limited by one or more of the physical configuration of the ATE and/or the physical and visual steps of confirmation by a human operator. This conventional solution for determining whether pins are properly assigned to ATE test ports is a manual process which is tedious and prone to human error.
For instance, the number of pins or pads of the IC/SOC to be tested may not match, i.e., the pins or pads may simply not have been adequately or accurately defined in relation to the test channels or ports provided by an ATE. Similarly, the number of pins or pads may be less or more than the number of test channels or ports provided by an ATE, or the ATE test program. Alternatively, it is possible that pins or pads may have been overlooked during the manual assignment of pins to ports in a “multi-port” test environment. Eventually, these pins or pads may be found, manually or by a computer, but usually with a time delay and the associated “cost” thereof.
Note as used herein, the terms “pin” or “pad” are used to refer first to either or both sorts of electrical communication devices. Hereafter, reference to a pin thus also refers to and includes reference to a pad, and vice versa, reference to a pad refers to and includes a pin. Also these terms are intended to refer collectively to both a physical site, which serves as an electrical contact for an IC and/or an SOC, as well as circuitry associated with the physical site for enabling electrical communication between components of the IC and/or SOC and components external to the IC and/or SOC.
The IC and/or SOC includes at least a first pin or pad disposed to electrically communicate with at least a portion of the ATE, with the first pin or pad being configured as a signal interface for components external to the IC/SOC. These may thus form systems for measuring a parameter of or communicated through a pin or pad of an IC/SOC. Preferably, such systems include automated test equipment (ATE) configured to electrically interconnect with the IC/SOC and to provide at least one signal to the IC and/or SOC. The IC and/or SOC is adapted to electrically communicate with the ATE so that, in response to receiving a test signal from the ATE, a response is then communicated back to the ATE which then measures at least one parameter of or communicated through the first pin. An ATE test protocol which is adapted to measure at least one parameter of or communicated through the first pin is also provided.
Note further that automated test equipment (ATE) typically provides the ability to test a wide variety of integrated circuits (ICs) and/or systems on chips (SOCs) using a wide variety of tests. For example, and not by means of limitation, the following test capability may be provided by the ATE, including: the ability to measure time, voltage, current, resistance, capacitance, inductance, frequency and/or jitter; the ability to measure, at specified times, voltage, current, resistance, capacitance, inductance, frequency and/or jitter; the ability to provide data; the ability to drive data at specified times; the ability to receive data; the ability to receive data at specified times; the ability to provide reference voltage; the ability to sink or source current; the ability to provide high impedance; and the ability to calibrate in relation of the ATE to the IC/SOC, among others.
As utilized herein, the term IC hereafter is intended to include and refer to an SOC as well, and the reverse is also intended, vice versa, i.e., the term SOC may also be used to refer to and include an IC. Note, SOCs may be considered special kinds of ICs wherein SOCs are devices which may contain an assortment of one or more circuit features such as intellectual property (IP) blocks including, for example, logic cores, memories, embedded processors, and/or a range of mixed-signal and RF cores to support voice, video, audio and/or data communications. Thus, SOCs may represent a sort of IC integration, where stand-alone IC chipsets are merged into a few or even into a single SOC. To save on development costs, several SOC vendors today are creating converged ICs that include a wide range of computational, communication, and/or entertainment functionality. Such devices may require many or all of these capabilities because their jobs may include obtaining data and/or executable code from or through various communication methods and/or protocols, decoding that data and/or code and then displaying, distributing and/or storing that data and/or executing the code to operate in accordance therewith.
However, given that these converged SOCs may be highly elastic in the capabilities they will provide, the exact test requirements for each SOC is a function of the IP blocks integrated therein and the test strategies defined by the engineering staff. Also, these converged SOCs will typically require a full gamut of testing capabilities; from RF and mixed signal to high-speed digital, memory, and scan test. To test the various IP blocks using traditional ATE equipment often requires multiple insertions utilizing multiple point solution testers. This may not present a cost-effective approach for many consumer-oriented devices. To keep test costs under control, one optimal solution may be to use one test platform that provides a full range of test resources. Creating and maintaining one general test program for a single platform may be much less expensive than having to deal with multiple test programs and/or platforms. Moreover, the use of one test platform offers an opportunity to test IP blocks in parallel, opening the way for higher levels of concurrent testing, and test-time efficiencies.
Parallel or concurrent test strategies can be enhanced by the use of a plurality of otherwise separate ports or channels in the ATE. A port is a connection on or from the ATE to a collection of one or more pins in/on the IC/SOC. Independent tests may then be performed concurrently or in parallel using separate ports so long as the pins are properly and separately assigned to separate ports. For example, a certain first set pins on an SOC may be dedicated to a particular IP core on the SOC, and a second set of pins may similarly be separately dedicated to a second particular IP core on the same SOC; then, each of these sets of pins may then be assigned to separate ports on the ATE, and thus provide for separate and parallel, i.e., non-sequential testing of those two IP cores. This can then reduce test time. Reduced test time assumes however, that the pins are properly assigned to the appropriate ATE ports during test set-up.
Thus, there is a need for improved systems and methods which address this and other issues of the prior art.